1. Field of the Invention
The present invention relates to a method for manufacturing a semiconductor device and, more particularly, to a method for forming a metallization structure having a substantially flat surface on a semiconductor substrate.
2. Description of the Prior Art
The packing density of semiconductor devices such as integrated circuits has been progressively increasing. For this purpose, the packing density of the metallization layer must be inevitably increased. For example, circuit elements formed in a semiconductor substrate often have only a low packing density when observed after the metallization layer is removed. This is because the packing density of the metallization layer is low, so the packing density of the semiconductor elements also becomes low.
The packing density of the metallization layer can be greatly improved by forming the metallization layer into a multi-layered structure in addition to micropatterning thereof.
In order to form a multi-layered metallization structure, metallization layers on the underlying metallization layers must not be disconnected at stepped portions. For this purpose, the underlying layer is tapered or an insulating interlayer has a slope in a sharp step of the underlying layer. In order to micropattern the metallization layer and obtain a multi-layered metallization structure, it is desired that the metallization layer and insulating layer be formed into a structure having a flat surface.
The present invention is mainly concerned with flattening of the metallization structure.
In a conventional method, anodic oxidation is utilized to form a metallization layer having a flat surface. According to this method, a metal layer is partially converted to an oxide by anodic oxidation. A remaining metal portion which is not oxidized constitutes an interconnection layer. According to this method, a height of a step is decreased as compared with the interconnection layer formed by etching. However, when a stepped portion is present in the underlying layer, the metal layer is abnormally oxidized at its portion corresponding to such a stepped portion, resulting in disconnection of the resultant interconnection layer. Alternatively, the metal is partially left nonoxidized depending on the interconnection layer pattern to be formed. Metals suitable for anodic oxidation are limited to aluminum, alloys thereof, and tantalum.
Another method for forming a flat metallization structure is described in Japanese patent publication No. 51-44871 published on Dec. 1, 1976. According to this method, a thermosetting resin film such as polyimide resin film is used as an insulating interlayer. This method includes the step of forming a polyimide resin film to cover the entire surface of a semiconductor substrate having a first metallization layer thereon. A contact hole is formed in the polyimide resin film by using a proper mask. After the mask is removed, a second metallization layer is formed on the polyimide resin film. According to this method, the polyimide resin covers the first metallization layer projected on the surface of the semiconductor substrate. Therefore, at an intersection between the first and second metallization layers through the polyimide resin film, substantially no stepped portion is formed. Therefore, according to this method, a multi-layered metallization structure having a substantially flat surface can be formed.
However, according to the above method, since some polyimide resin remains as an insulating layer in the final semiconductor product, some problems are presented. First, the polyimide resin is hygroscopic, so that a semiconductor device encapsulated in a compact plastic package has low resistance to moisture. Second, the polyimide resin tends to be polarized by a bias voltage applied to the semiconductor device. As a result, the electrical characteristics of the semiconductor device tend to vary, thus degrading operation reliability.